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Figure 8-25 Specific End-of-Interrupt Register (EOI, offset 22h). . . . . . . . . . . . . . . . . . . . . 8-36
Figure 8-26 Interrupt Vector Register (INTVEC, offset 20h) . . . . . . . . . . . . . . . . . . . . . . . . 8-37
Figure 9-1 Timer 0 and Timer 1 Mode and Control Registers (T0CON, T1CON,
offsets 56h and 5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Figure 9-2 Timer 2 Mode and Control Register (T2CON, offset 66h) . . . . . . . . . . . . . . . . . 9-5
Figure 9-3 Timer Count Registers (T0CNT, T1CNT, T2CNT, offsets 50h, 58h, and 60h) . . 9-6
Figure 9-4 Timer Maxcount Compare Registers (T0CMPA, T0CMPB, T1CMPA,
T1CMPB, T2CMPA, offsets 52h, 54h, 5Ah, 5Ch, and 62h) . . . . . . . . . . . . . . . . 9-7
Figure 10-1 DMA Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Figure 10-2 DMA Control Registers (D0CON, D1CON, offsets CAh and DAh) . . . . . . . . . 10-3
Figure 10-3 DMA Transfer Count Registers (D0TC, D1TC, offsets C8h and D8h) . . . . . . . 10-5
Figure 10-4 DMA Destination Address High Register
(D0DSTH, D1DSTH, offsets C6h and D6h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Figure 10-5 DMA Destination Address Low Register
(D0DSTL, D1DSTL, offsets C4h and D4h). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Figure 10-6 DMA Source Address High Register
(D0SRCH, D1SRCH, offsets C2h and D2h). . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Figure 10-7 DMA Source Address Low Register
(D0SRCL, D1SRCL, offsets C0h and D0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Figure 10-8 Source-Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Figure 10-9 Destination Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Figure 11-1 Serial Port Control Register (SPCT, offset 80h) . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Figure 11-2 Serial Port Status Register (SPSTS, offset 82h) . . . . . . . . . . . . . . . . . . . . . . . 11-4
Figure 11-3 Serial Port Transmit Data Register (SPTD, offset 84h) . . . . . . . . . . . . . . . . . . 11-5
Figure 11-4 Serial Port Receive Data Register (SPRD, offset 86h) . . . . . . . . . . . . . . . . . . 11-6
Figure 11-5 Serial Port Baud Rate Divisor Register (SPBAUD, offset 88h) . . . . . . . . . . . . 11-7
Figure 12-1 Synchronous Serial Status Register (SSS, offset 10h) . . . . . . . . . . . . . . . . . . 12-3
Figure 12-2 Synchronous Serial Control Register (SSC, offset 12h). . . . . . . . . . . . . . . . . . 12-4
Figure 12-3 Synchronous Serial Transmit Register (SSD1, SSD0, offsets 14h and 16h) . . 12-5
Figure 12-4 Synchronous Serial Receive Register (SSR, offset 18h) . . . . . . . . . . . . . . . . . 12-6
Figure 12-5 Synchronous Serial Interface Multiple Write . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Figure 12-6 Synchronous Serial Interface Multiple Read . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Figure 13-1 Programmable I/O Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Figure 13-2 PIO Mode 1 Register (PIOMODE1, offset 76h) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Figure 13-3 PIO Mode 0 Register (PIOMODE0, offset 70h) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Figure 13-4 PIO Direction 1 Register (PDIR1, offset 78h). . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Figure 13-5 PIO Direction 0 Register (PDIR0, offset 72h). . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Figure 13-6 PIO Data 1 Register (PDATA1, offset 7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Figure 13-7 PIO Data 0 Register (PDATA0, offset 74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Figure A-1 Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4