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Register Summary
A-6
Figure A-1 Internal Register Summary (continued)
15 7 0
DINC
DDEC
SM/IO
SINC
SDEC
B/WSTCHGResTC INT SYN P
TDRQ
DMA 0 Control Register (D0CON)
Page 10-3
CA
DM/IO
15 7 0
TC15–TC0
DMA 0 Transfer Count Register (D0TC)
Page 10-5
C8
15 7 0
Reserved
DDA19–DDA16
DMA 0 Destination Address High Register (D0DSTH)
Page 10-6
C6
15 7 0
DDA15–DDA0
DMA 0 Destination Address Low Register (D0DSTL)
Page 10-7
C4
15
70
Reserved
DSA19–DSA16
DMA 0 Source Address High Register (D0SRCH)
Page 10-8
C2
15
70
DSA15–DSA0
DMA 0 Source Address Low Register (D0SRCL)
Page 10-9
C0