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Index I-5
Master mode, 8-16
INT2 signal (Maskable Interrupt Request 2), 3-6
INT3 Control Register
Master mode, 8-16
INT3 signal (Maskable Interrupt Request 3), 3-6
INT4 Control Register
Master mode, 8-17
INT4 signal (Maskable Interrupt Request 4), 3-6
INTA0 signal (Interrupt Acknowledge 0), 3-6
INTA1 signal (Interrupt Acknowledge 1), 3-6
Integer data type, 2-8
Internal memory
debug modes, 6-2
disable, 6-2
external RAM interaction, 6-1
show read enable, 6-2
Interrupt acknowledge, 8-8
Interrupt conditions and sequence, 8-4
Interrupt control unit, 8-1
Interrupt controller registers
Master mode, 8-13
Slave mode, 8-29
Interrupt controller reset conditions, 8-9
Interrupt enable flag (IF), 8-2
Interrupt mask bit, 8-2
Interrupt Mask Register
Master mode, 8-25
Slave mode, 8-35
Interrupt priority, 8-2, 8-5
Interrupt Request Register
Master mode, 8-22
Slave mode, 8-32
Interrupt return (IRET), 8-4
Interrupt Status Register
Master mode, 8-21
Slave mode, 8-31
Interrupt Vector Register
Slave mode, 8-37
Interrupt vector table, 8-1
Interrupt-Enable Flag bit, 2-3
Interrupts
array BOUNDs exception, 8-7
breakpoint, 8-7
cascade mode, 8-11
divide error exception, 8-6
EOI, 8-12
ESC opcode exception, 8-7
fully nested mode, 8-10
Instruction exceptions, 8-3
INTO overflow detected, 8-7
Maskable and nonmaskable, 8-2
Master mode operation, 8-10
nonmaskable (NMI), 8-6
polled, 8-12
Slave mode, 8-29
Slave mode nesting, 8-29
Special fully nested mode, 8-12
trace, 8-6
types, 8-1, 8-6
types, table of, 8-3
unused opcode, 8-7
IREQ bit (Interrupt Request)
Poll Register, 8-27
Poll Status Register, 8-26
IRET, 8-4
IRQ signal (Slave Interrupt Request), 3-6
K
Key features and benefits, 1-1
L
L2-L0 field (Interrupt Type), 8-36
LB2-LB0 field (Lower Boundary), 5-4
LCS signal (Low Memory Chip Select), 3-7
LOOP bit (Loopback), 11-2
Low Memory Chip Select Register, 5-6
LTM bit (Level-Triggered Mode)
INT0 Control Register, 8-14
INT1 Control Register, 8-14
INT2 Control Register, 8-16
INT3 Control Register, 8-16
INT4 Control Register, 8-17
M
M/IO bit (Memory/I/O Space), 4-4
M6-M0 field (MCS Block Size), 5-10
M6-M0 field (Refresh Base), 7-1
Maskable interrupts, 8-2
Master mode operation, 8-10
MC bit (Maximum Count Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
MCS2-MCS0 signals (Midrange Memory Chip Selects
2-0), 3-7
MCS3 signal (Midrange Memory Chip Select 3), 3-7
Memory
addressing modes, 2-10
interface, 1-7
operands, 2-10
organization, 2-3
Memory Partition Register, 7-1