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Register Summary
A-4
Figure A-1 Internal Register Summary
15 7 0
Res S/M
R19–R8
Res M/IO
Peripheral Control Block Relocation Register (RELREG)
Page 4-4
Offset
(Hexadecimal)
FE
Reset Configuration Register (RESCON)
Page 4-5
F6
15 7 0
RC
Processor Release Level Register (PRL)
Page 4-6
F4
15 7 0
PRL
Reserved
CAF
CAD
15 7 0
CBD
Power-Save Control Register (PDCON)
Page 4-7
F2–F0
PSEN
F0
000
00000
CBF
15
70
00000
T8–T0
0E
Enable RCU Register (EDRAM)
Page 7-2
E4
15
70
000000
RC8–RC0
0
Clock Prescaler Register (CDRAM)
Page 7-2
E2