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Timer Control Unit
9-6
9.2.4 Timer Count Registers
(T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h)
These registers can be incremented by one every four internal processor clocks. Timer 0
and timer 1 can also be configured to increment based on the TMRIN0 and TMRIN1 external
signals, or they can be prescaled by timer 2. See Figure 9-3.
The count registers are compared to maximum count registers and various actions are
triggered based on reaching a maximum count.
Figure 9-3 Timer Count Registers (T0CNT, T1CNT, T2CNT, offsets 50h, 58h, and 60h)
The value of these registers at reset is undefined.
Bits 15–0: Timer Count Value (TC15–TC0)—This register contains the current count of
the associated timer. The count is incremented every fourth processor clock in internal
clocked mode, or each time the timer 2 maxcount is reached if prescaled by timer 2. Timer
0 and timer 1 can be configured for external clocking based on the TMRIN0 and TMRIN1
signals.
15
70
TC15–TC0