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C-53
REGISTERS
T1CONTROL
T1CONTROL
Address:
Reset State:
1F78H
00H
The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count
rate for timer 1.
7 0
CE UD M2 M1 M0 P2 P1 P0
Bit
Number
Bit
Mnemonic
Function
7 CE Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
6 UD Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
0 = count down
1 = count up
5:3 M2:0 EPA Clock Direction Mode Bits
These bits determine the timer clocking source and direction control
source.
M2 M1 M0 Clock Source Direction Source
000F
XTAL1
/4 UD bit (T1CONTROL.6)
X 0 1 T1CLK pin
†
UD bit (T1CONTROL.6)
010F
XTAL1
/4 T1DIR pin
011T1CLK pin
†
T1DIR pin
111quadrature clocking using T1CLK and T1DIR
†
If an external clock is selected, the timer counts on both the rising
and falling edges of the clock.
2:0 P2:0 EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2 P1 P0 Prescaler Divisor Resolution
†
000divide by 1 (disabled) 250 ns
001divide by 2 500 ns
010divide by 4 1 µs
011divide by 8 2 µs
100divide by 16 4 µs
101divide by 32 8 µs
110divide by 64 16 µs
111enable T1RELOAD —
†
At 16 MHz. Use the formula on page 11-6 to calculate the resolution
at other frequencies.