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11-5
EVENT PROCESSOR ARRAY (EPA)
11.3 TIMER/COUNTER FUNCTIONAL OVERVIEW
The EPA has two 16-bit up/down timer/counters, timer 1 and timer 2, which can be clocked in-
ternally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked
externally. Figure 11-2 illustrates the timer/counter structure.
PI_MASK 1FBCH 1FBCH 1FBCH Peripheral Interrupt Mask
The bits in this register enable and disable (mask)
the timer 1 and 2 overflow/underflow interrupt
requests, the waveform generator interrupt request
(MC, MD), the EPA compare-only channel 5
interrupt request ( MD), and the serial port error
interrupts (MH).
PI_PEND 1FBEH 1FBEH 1FBEH Peripheral Interrupt Pending
Any bit set indicates a pending interrupt request.
T1CONTROL 1F78H 1F78H 1F78H Timer 1 Control
This register enables/disables timer 1, controls
whether it counts up or down, selects the clock
source and direction, and determines the clock
prescaler setting.
T1RELOAD 1F72H 1F72H 1F72H Timer 1 Reload
This register contains an initialization value for
timer 1. A timer 1 overflow or underflows loads the
T1RELOAD value into the TIMER1 register if both
quadrature clocking and the reload function are
enabled (T1CONTROL.5:0 = 1).
T2CONTROL 1F7CH 1F7CH 1F7CH Timer 2 Control
This register enables/disables timer 2, controls
whether it counts up or down, selects the clock
source and direction, and determines the clock
prescaler setting.
TIMER1 1F7AH 1F7AH 1F7AH Timer 1 Value
This register contains the current value of timer 1.
TIMER2 1F7EH 1F7EH 1F7EH Timer 2 Value
This register contains the current value of timer 2.
Table 11-3. EPA Control and Status Registers (Continued)
Mnemonic
Address
Description
MC MD MH