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A-35
INSTRUCTION SET REFERENCE
SHRAL ARITHMETIC RIGHT SHIFT DOUBLE-
WORD. Shifts the destination double-word
operand to the right as many times as
specified by the count operand. The count
may be specified either as an immediate
value in the range of 0 to 15 (0FH), inclusive,
or as the content of any register (10H –
0FFH) with a value in the range of 0 to 31
(1FH), inclusive. If the original high order bit
value was “0,” zeros are shifted in. If the
value was “1,” ones are shifted in.
Te mp
← (COUNT)
do while Temp
≠ 0
C
← Low order bit of (DEST)
(DEST)
← (DEST)/2
Te mp
← Temp – 1
end_while
SHRAL lreg, #count
(00001110) (count) (lreg)
or
SHRAL lreg, breg
(00001110) (breg) (lreg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
In this operation, (DEST)/2 rep-
resents signed division.
PSW Flag Settings
ZNCVVTST
✓✓✓0—✓
SHRB LOGICAL RIGHT SHIFT BYTE. Shifts the
destination byte operand to the right as many
times as specified by the count operand. The
count may be specified either as an
immediate value in the range of 0 to 15
(0FH), inclusive, or as the content of any
register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. The left bits
of the result are filled with zeros. The last bit
shifted out is saved in the carry flag.
Te mp
← (COUNT)
do while Temp
≠ 0
C
← Low order bit of (DEST)
(DEST)
← (DEST)/2
Te mp
← Temp–1
end_while
SHRB breg, #count
(00011000) (count) (breg)
or
SHRB breg, breg
(00011000) (breg) (breg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
In this operation, (DEST)/2 rep-
resents unsigned division.
PSW Flag Settings
ZNCVVTST
✓0✓0—✓
Table A-6. Instruction Set (Continued)
Mnemonic Operation Instruction Format