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INDEX
Index-5
N
N flag, 5-9, 5-19
Noise reduction, 11-2, 11-3, 11-5
Nonpage mode
bus cycles, See External bus cycles, Nonpage
mode
bus structure, 13-1
configuration, 4-8
design example, 13-22, 13-26
port pin status, 13-16
Nonpage Mode Bus Cycles, 13-4
Nonvolatile memory
programming and verifying, 14-1–14-9
NOP instruction, 5-15, A-25
O
On-chip code memory, 3-2, 13-8
accessing in data memory, 4-16
accessing in region 00:, 3-9
idle mode, 12-4
powerdown mode, 12-5
programming and verifying, 14-1, 14-7
setup for programming and verifying, 14-3–
14-5
starting address, 3-8, 14-2
top eight bytes, 3-9, 14-2
See also OTPROM/EPROM, ROM
On-chip oscillator
hardware setup, 11-1
On-chip RAM, 3-2, 3-8
bit addressable, 3-8, 5-11
bit addressable in MCS 51 architecture, 5-11
idle mode, 12-4
MCS 51 architecture, 3-3, 3-4
reset, 11-6
ONCE mode, 12-1, 12-7
entering, 12-7
exiting, 12-7
Opcodes
for binary and source modes, 4-13, 5-1
map, A-4
binary mode, 4-15
source mode, 4-15
See also Binary and source modes
ORL instruction, 5-9, 5-11
for bits, A-23
ORL/ instruction, 5-11
for bits, A-23
Oscillator, 2-6
at startup, 11-7
during reset, 11-5
on-chip, 11-3
ONCE mode, 12-7
powerdown mode, 12-5, 12-6
programming and verifying nonvolatile
memory, 14-3
OTPROM/EPROM (on-chip)
programming algorithm, 14-5
programming and verifying, 14-3
verify algorithm, 14-6
See also On-chip code memory, Configuration
bytes, Lock bits, Encryption array,
Signature bytes
OV bit, 5-18, 5-19, C-20
Overflow See OV bit
P
P bit, 5-18, C-20
P0, 3-17, 3-18, 7-2, C-2, C-3, C-17
P1, 3-17, 3-18, 7-2, C-2, C-3, C-17
P2, 3-17, 3-18, 7-2, C-2, C-3, C-18
P3, 3-17, 3-18, 7-2, C-2, C-3, C-18
Page mode, 2-5
address access time, 13-6
bus cycles, See External bus cycles, page
mode
configuration, 4-8
design example, 13-20, 13-29
port pin status, 13-17
PAGE# bit, 4-8
PCA
compare/capture modules, 9-1
idle mode, 12-4
pulse width modulation, 9-11
SFRs, 3-19, C-5
timer/counter, 9-1
watchdog timer, 9-1, 9-9
PCON, 3-17, 3-18, 10-7, 12-1, 12-2, 12-5, C-2, C-
3, C-19
idle mode, 12-4
powerdown mode, 12-6
reset, 11-6
Peripheral cycle, 2-6
Phase 1 and phase 2, 2-6