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8XC251SA, SB, SP, SQ USER’S MANUAL
12-6
12.4.1 Entering Powerdown Mode
To enter powerdown mode, set the PCON register PD bit. The 8XC251Sx enters the power-down
mode upon execution of the instruction that sets the PD bit. The instruction that sets the PD bit is
the last instruction executed.
12.4.2 Exiting Powerdown Mode
CAUTION
If V
CC
was reduced during the powerdown mode, do not exit powerdown until
V
CC
is restored to the normal operating level.
There are two ways to exit the powerdown mode:
• Generate an enabled external interrupt. Hardware clears the PD bit in the PCON register
which starts the oscillator and restores the clocks to the CPU and peripherals. Execution
resumes with the interrupt service routine. Upon completion of the interrupt service routine,
program execution resumes with the instruction immediately following the instruction that
activated powerdown mode.
NOTE
To enable an external interrupt, set the IE register EX0 and/or EX1 bit[s]. The
external interrupt used to exit powerdown mode must be configured as level
sensitive and must be assigned the highest priority. In addition, the duration of
the interrupt must be of sufficient length to allow the oscillator to stabilize.
• Generate a reset. See section 11.4, “Reset.” A logic high on the RST pin clears the PD bit in
the PCON register directly and asynchronously. This starts the oscillator and restores the
clocks to the CPU and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated powerdown and may
continue for a number of clock cycles before the internal reset algorithm takes control.
Reset initializes the 8XC251Sx and vectors the CPU to address FF:0000H.
NOTE
During the time that execution resumes, the internal RAM cannot be accessed;
however, it is possible for the port pins to be accessed. To avoid unexpected
outputs at the port pins, the instruction immediately following the instruction
that activated the powerdown mode should not write to a port pin or to the
external RAM.