Filter
Top Products
8XC251SA, SB, SP, SQ USER’S MANUAL
6-14
6.7.2.4 Blocking Conditions
If all enable and priority requirements have been met, a single prioritized interrupt request at a
time generates a vector cycle to an interrupt service routine (refer to the CALL instructions in Ap-
pendix A, “Instruction Set Reference”). There are three causes of blocking conditions with hard-
ware-generated vectors:
1. An interrupt of equal or higher priority level is already in progress (defined as any point
after the flag has been set and the RETI of the ISR has not executed).
2. The current polling cycle is not the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write to the IE0, IPH0, or IPL0 registers.
Any of these conditions blocks calls to interrupt service routines. Condition two ensures the in-
struction in progress completes before the system vectors to the ISR. Condition three ensures at
least one more instruction executes before the system vectors to additional interrupts if the in-
struction in progress is a RETI or any write to IE0, IPH0, or IPL0. The complete polling cycle is
repeated every four state times.
6.7.2.5 Interrupt Vector Cycle
When an interrupt vector cycle is initiated, the CPU breaks the instruction stream sequence, re-
solves all instruction pipeline decisions, and pushes multiple program counter (PC) bytes onto the
stack. The CPU then reloads the PC with a start address for the appropriate ISR. The number of
bytes pushed to the stack depends upon the INTR bit in the UCONFIG1 configuration byte (see
Figure 4-4 on page 4-7). The complete sample, poll, request and context switch vector sequence
is illustrated in the interrupt latency timing diagram (Figure 6-5
).
NOTE
If the interrupt flag for a level-triggered external interrupt is set but denied for
one of the above conditions and is clear when the blocking condition is
removed, then the denied interrupt is ignored. In other words, blocked interrupt
requests are not buffered for retention.