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12-5
SPECIAL OPERATING MODES
12.3.2 Exiting Idle Mode
There are two ways to exit idle mode:
• Generate an enabled interrupt. Hardware clears the PCON register IDL bit which restores
the clocks to the CPU. Execution resumes with the interrupt service routine. Upon
completion of the interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated idle mode. The general purpose flags
(GF1 and GF0 in the PCON register) may be used to indicate whether an interrupt occurred
during normal operation or during idle mode. When idle mode is exited by an interrupt, the
interrupt service routine may examine GF1 and GF0.
• Reset the chip. See section 11.4, “Reset.” A logic high on the RST pin clears the IDL bit in
the PCON register directly and asynchronously. This restores the clocks to the CPU.
Program execution momentarily resumes with the instruction immediately following the
instruction that activated the idle mode and may continue for a number of clock cycles
before the internal reset algorithm takes control. Reset initializes the 8XC251Sx and vectors
the CPU to address FF:0000H.
NOTE
During the time that execution resumes, the internal RAM cannot be accessed;
however, it is possible for the port pins to be accessed. To avoid unexpected
outputs at the port pins, the instruction immediately following the instruction
that activated idle mode should not write to a port pin or to the external RAM.
12.4 POWERDOWN MODE
The powerdown mode places the 8XC251Sx in a very low power state. Powerdown mode stops
the oscillator and freezes all clocks at known states (Figure 12-2). The CPU status prior to enter-
ing powerdown mode is preserved, i.e., the program counter, program status word register, and
register file retain their data for the duration of powerdown mode. In addition, the SFRs and RAM
contents are preserved. The status of the port pins depends on the location of the program mem-
ory:
• Internal program memory: the ALE and PSEN# pins are pulled low and the ports 0, 1, 2,
and 3 pins are reading data (Table 12-1).
• External program memory: the ALE and PSEN# pins are pulled low; the port 0 pins are
floating; and the pins of ports 1, 2, and 3 are reading data (Table 12-1).
NOTE
Vcc may be reduced to as low as 2 V during powerdown to further reduce
power dissipation. Take care, however, that Vcc is not reduced until power-
down is invoked.