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C-11
REGISTERS
CMOD
Address: S:D9H
Reset State: 00XX X000B
PCA Timer/Counter Mode Register. Contains bits for selecting the PCA timer/counter input, disabling
the PCA timer/counter during idle mode, enabling the PCA WDT reset output (module 4 only), and
enabling the PCA timer/counter overflow interrupt.
7 0
CIDL WDTE — — — CPS1 CPS0 ECF
Bit
Number
Bit
Mnemonic
Function
7 CIDL PCA Timer/Counter Idle Control:
CIDL = 1 disables the PCA timer/counter during idle mode. CIDL = 0
allows the PCA timer/counter to run during idle mode.
6 WDTE Watchdog Timer Enable:
WDTE = 1 enables the watchdog timer output on PCA module 4.
WDTE = 0 disables the PCA watchdog timer output.
5:3 — Reserved:
The values read from these bits are indeterminate. Write zeros to these
bits.
2:1 CPS1:0 PCA Timer/Counter Input Select:
CPS1 CPS0
00F
OSC
/12
01F
OSC
/4
1 0 Timer 0 overflow
1 1 External clock at ECI pin (maximum rate = F
OSC
/8 )
0 ECF PCA Timer/Counter Interrupt Enable:
ECF = 1 enables the CF bit in the CCON register to generate an interrupt
request.