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FIGURES
Figure Page
8-12 T2CON: Timer 2 Control Register..............................................................................8-17
9-1 Programmable Counter Array.......................................................................................9-3
9-2 PCA 16-bit Capture Mode............................................................................................9-6
9-3 PCA Software Timer and High-speed Output Modes...................................................9-8
9-4 PCA Watchdog Timer Mode.......................................................................................9-10
9-5 PCA 8-bit PWM Mode ................................................................................................9-11
9-6 PWM Variable Duty Cycle..........................................................................................9-12
9-7 CMOD: PCA Timer/Counter Mode Register...............................................................9-13
9-8 CCON: PCA Timer/Counter Control Register.............................................................9-14
9-9 CCAPMx: PCA Compare/Capture Module Mode Registers.......................................9-15
10-1 Serial Port Block Diagram ..........................................................................................10-2
10-2 SCON: Serial Port Control Register ...........................................................................10-3
10-3 Mode 0 Timing............................................................................................................10-5
10-4 Data Frame (Modes 1, 2, and 3) ................................................................................10-6
10-5 Timer 2 in Baud Rate Generator Mode ....................................................................10-13
11-1 Minimum Setup ..........................................................................................................11-1
11-2 CHMOS On-chip Oscillator.........................................................................................11-3
11-3 External Clock Connection.........................................................................................11-4
11-4 External Clock Drive Waveforms................................................................................11-5
11-5 Reset Timing Sequence.............................................................................................11-8
12-1 Power Control (PCON) Register.................................................................................12-2
12-2 Idle and Powerdown Clock Control ............................................................................12-3
13-1 Bus Structure in Nonpage Mode and Page Mode......................................................13-1
13-2 External Code Fetch (Nonpage Mode).......................................................................13-4
13-3 External Data Read (Nonpage Mode)........................................................................13-4
13-4 External Data Write (Nonpage Mode) ........................................................................13-5
13-5 External Code Fetch (Page Mode).............................................................................13-6
13-6 External Data Read (Page Mode) ..............................................................................13-7
13-7 External Data Write (Page Mode)...............................................................................13-7
13-8 External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) .......................13-9
13-9 External Data Write (Nonpage Mode, One WR# Wait State).....................................13-9
13-10 External Code Fetch (Nonpage Mode, One ALE Wait State)...................................13-10
13-11 Real-time Wait State Control Register (WCON).......................................................13-11
13-12 External Code Fetch/Data Read (Nonpage Mode, RT Wait State)..........................13-13
13-13 External Data Write (Nonpage Mode, RT Wait State)..............................................13-13
13-14 External Data Read (Page Mode, RT Wait State)....................................................13-14
13-15 External Data Write (Page Mode, RT Wait State)....................................................13-14
13-16 Configuration Byte Bus Cycles.................................................................................13-15
13-17 Bus Diagram for Example 1: 80C251SB in Page Mode...........................................13-18
13-18 Address Space for Example 1..................................................................................13-19
13-19 Bus Diagram for Example 2: 80C251SB in Page Mode...........................................13-20
13-20 Address Space for Example 2..................................................................................13-21
13-21 Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode ..................13-22
13-22 Address Space for Example 3..................................................................................13-23