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8XC251SA, SB, SP, SQ USER’S MANUAL
9-10
The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset,
the user has three options:
• periodically change the comparison value in CCAP4H/CCAP4L so a match never occurs
• periodically change the PCA timer/counter value so a match never occurs
• disable the module 4 reset output signal by clearing the WDTE bit before a match occurs,
then later re-enable it
The first two options are more reliable because the WDT is not disabled as in the third option.
The second option is not recommended if other PCA modules are in use, since the five modules
share a common time base. Thus, in most applications the first option is the best one.
Figure 9-4. PCA Watchdog Timer Mode
A4165-01
CCAP4H
(8 Bits)
CCAP4L
(8 Bits)
CH
(8 Bits)
CL
(8 Bits)
X ECOM4 0 0 X 0 X
1
WDTE
PCA Timer/Counter
PCA WDT Reset
07
CCAPM4
Mode Register
X = Don't Care
Compare/Capture
Module
16-Bit
Comparator
Count
Input
Reset
Write to
CCAP4L
"0"
Match
"1"
Write to CCAP4H
Enable
CMOD.6