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CONTENTS
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5.4 BIT INSTRUCTIONS ................................................................................................... 5-11
5.4.1 Bit Addressing .........................................................................................................5-11
5.5 CONTROL INSTRUCTIONS ....................................................................................... 5-12
5.5.1 Addressing Modes for Control Instructions .............................................................5-13
5.5.2 Conditional Jumps ..................................................................................................5-14
5.5.3 Unconditional Jumps ...............................................................................................5-15
5.5.4 Calls and Returns ...................................................................................................5-15
5.6 PROGRAM STATUS WORDS .................................................................................... 5-16
CHAPTER 6
INTERRUPT SYSTEM
6.1 OVERVIEW ................................................................................................................... 6-1
6.2 8XC251SA, SB, SP, SQ INTERRUPT SOURCES........................................................ 6-3
6.2.1 External Interrupts .....................................................................................................6-3
6.2.2 Timer Interrupts .........................................................................................................6-4
6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT........................................ 6-5
6.4 SERIAL PORT INTERRUPT.......................................................................................... 6-5
6.5 INTERRUPT ENABLE................................................................................................... 6-5
6.6 INTERRUPT PRIORITIES............................................................................................. 6-7
6.7 INTERRUPT PROCESSING ......................................................................................... 6-9
6.7.1 Minimum Fixed Interrupt Time ................................................................................6-10
6.7.2 Variable Interrupt Parameters .................................................................................6-10
6.7.2.1 Response Time Variables ..................................................................................6-10
6.7.2.2 Computation of Worst-case Latency With Variables ..........................................6-12
6.7.2.3 Latency Calculations ..........................................................................................6-13
6.7.2.4 Blocking Conditions ............................................................................................6-14
6.7.2.5 Interrupt Vector Cycle ........................................................................................6-14
6.7.3 ISRs in Process ......................................................................................................6-15
CHAPTER 7
INPUT/OUTPUT PORTS
7.1 INPUT/OUTPUT PORT OVERVIEW............................................................................. 7-1
7.2 I/O CONFIGURATIONS................................................................................................. 7-2
7.3 PORT 1 AND PORT 3 ................................................................................................... 7-2
7.4 PORT 0 AND PORT 2 ................................................................................................... 7-2
7.5 READ-MODIFY-WRITE INSTRUCTIONS..................................................................... 7-5
7.6 QUASI-BIDIRECTIONAL PORT OPERATION.............................................................. 7-6
7.7 PORT LOADING............................................................................................................ 7-7
7.8 EXTERNAL MEMORY ACCESS................................................................................... 7-7
CHAPTER 8
TIMER/COUNTERS AND WATCHDOG TIMER
8.1 TIMER/COUNTER OVERVIEW..................................................................................... 8-1