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8XC251SA, SB, SP, SQ USER’S MANUAL
6-10
6.7.1 Minimum Fixed Interrupt Time
All interrupts are sampled or polled every four state times (see Figure 6-5). Two of eight inter-
rupts are latched and polled per state time within any given four state time window. One addition-
al state time is required for a context switch request. For code branches to jump locations in the
current 64-Kbyte memory region (compatible with MCS 51 microcontrollers), the context switch
time is 11 states. Therefore, the minimum fixed poll and request time is 16 states (4 poll states +
1 request state + 11 states for the context switch = 16 state times).
Therefore, this minimum fixed period rests upon four assumptions:
• The source request is an internal interrupt with high enough priority to take precedence over
other potential interrupts,
• The request is coincident with internal execution and needs no instruction completion time,
• The program uses an internal stack location, and
• The ISR is in on-chip OTPROM/ROM.
6.7.2 Variable Interrupt Parameters
Both response time and latency calculations contain fixed and variable components. By defini-
tion, it is often difficult to predict exact timing calculations for real-time requests. One large vari-
able is the completion time of an instruction cycle coincident with the occurrence of an interrupt
request. Worst-case predictions typically use the longest-executing instruction in an architecture’s
code set. In the case of the 8XC251Sx, the longest-executing instruction is a 16-bit divide (DIV).
However, even this 21- state instruction may have only 1 or 2 remaining states to complete before
the interrupt system injects a context switch. This uncertainty affects both response time and la-
tency.
6.7.2.1 Response Time Variables
Response time is defined as the start of a dynamic time period when a source requests an interrupt
and lasts until a break in the current instruction execution stream occurs (see Figure 6-5). Re-
sponse time (and therefore latency) is affected by two primary factors: the incidence of the re-
quest relative to the four-state-time sample window and the completion time of instructions in the
response period (i.e., shorter instructions complete earlier than longer instructions).
NOTE
External interrupt signals require one additional state time in comparison to
internal interrupts. This is necessary to sample and latch the pin value prior to
a poll of interrupts. The sample occurs in the first half of the state time and the
poll/request occurs in the second half of the next state time. Therefore, this
sample and poll/request portion of the minimum fixed response and latency