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9-3
PROGRAMMABLE COUNTER ARRAY
Setting the run control bit (CR in the CCON register) turns the PCA timer/counter on, if the out-
put of the NAND gate (Figure 9-1) equals logic 1. The PCA timer/counter continues to operate
during idle mode unless the CIDL bit of the CMOD register is set. The CPU can read the contents
of the CH and CL registers at any time. However, writing to them is inhibited while they are
counting (i.e., when the CR bit is set).
Figure 9-1. Programmable Counter Array
16-bit
Bus
CL
(8 Bits)
CH
(8 Bits)
CF
Interrupt
Request
F
OSC
/12
PCA
Timer/Counter
CCON.7
Overflow
ECF
CMOD.0
Enable
CR
CCON.6
Run Control
IDL
PCON.0
Idle Mode
CIDL
CMOD.7
CPS0
CMOD.1
CPS1
CMOD.2
00
01
10
11
F
OSC
/4
Timer 0 Overflow
P1.2/ECI
Module 0
P1.3/CEX0
Module 1
P1.4/CEX1
Module 2
P1.5/CEX2
Module 3
P1.6/CEX3/WAIT#
Module 4
P1.7/CEX4/
A17/WCLK
(16 Bits)
Compare/Capture
Modules
A4162-04
i_pca.fm5 Page 3 Thursday, June 27, 1996 1:39 PM