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8XC251SA, SB, SP, SQ USER’S MANUAL
8-10
3. Enter an eight-bit reload value (n
R
) in register TH0. This can be the same as n
0
or
different, depending on the application.
4. Set the TR0 bit in the TCON register (Figure 8-6) to start the timer. Timer overflow occurs
after FFH + 1 - n
0
peripheral cycles, setting the TF0 flag and loading n
R
into TL0 from
TH0. When the interrupt is serviced, hardware clears TF0.
5. The timer continues to overflow and generate interrupt requests every FFH + 1 - n
R
peripheral cycles.
6. To halt the timer, clear the TR0 bit.
8.5.2 Pulse Width Measurements
For timer 0 and timer 1, setting GATEx and TRx allows an external waveform at pin INTx# to
turn the timer on and off. This setup can be used to measure the width of a positive-going pulse
present at pin INTx#. Pulse width measurements using timer 0 in mode 1 can be made as follows:
1. Program the four low-order bits of the TMOD register (Figure 8-5) to specify: mode 1 for
timer 0, C/T0# = 0 to select F
OSC
/12 as the timer input, and GATE0 = 1 to select INT0 as
timer run control.
2. Enter an initial value of all zeros in the 16-bit timer register TH0/TL0, or read and store
the current contents of the register.
3. Set the TR0 bit in the TCON register (Figure 8-6) to enable INT0.
4. Apply the pulse to be measured to pin INT0. The timer runs when the waveform is high.
5. Clear the TR0 bit to disable INT0.
6. Read timer register TH0/TL0 to obtain the new value.
7. Calculate pulse width = 12 T
OSC
× (new value - initial value).
8. Example: F
OSC
= 16 MHz and 12T
OSC
= 750 ns. If the new value = 10,000
10
and the initial
value = 0, the pulse width = 750 ns × 10,000 = 7.5 ms.
8.6 TIMER 2
Timer 2 is a 16-bit timer/counter. The count is maintained by two eight-bit timer registers, TH2
and TL2, connected in cascade. The timer/counter 2 mode control register (T2MOD, as shown in
Figure 8-11 on page 8-16) and the timer/counter 2 control register (T2CON, as shown in Figure
8-12 on page 8-17) control the operation of timer 2.