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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1. Swapped AD23 and AD19 on 400 pin connector.
2. Separated CSEL on IDE0 and IDE1
3. Swapped pins 1 and 3 (V5 with TP) on CPU-Fan connector.
4. Tied VBAT (pin 65) to 5.0V on Super I/O.
5. Changed RP48 to 4.7K. (Pullups for mouse and keyboard.)
6. Inverted POWERON# signal (SUSC#) from PIIX4 to control soft-on feature.
7. Changed Bulk decoupling on +12 and -12 to 2x220uF from 2x400uF.
8. Changed Bulk decoupling cap C154 from 10uF to 47uF to reduce BOM line items.
Changes made to Revision C.
1. Tied VBAT (pin 65) to 3.3V on Super I/O.
Evaluation Platform
Revision D
History
Changes made to Revision B.
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT
BEEN VERIFIED FOR MANUFACTURING AS AN END USER
PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING
ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY
WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is
granted herein.
Intel disclaims all liability, including liability
for infringement of any proprietary rights, relating
to use of information in this specification. Intel
does not warrant or represent that such use will not
infringe such rights.
System Electronics Board
Changes made to Revision D.
1. Added Signals PWROK(A24) +12V(A33) MB12#_R(B33) to J19A.
2. Moved J20
3. Added C229 to -PCIRST
D
Changes
C
1 22Thursday, February 25, 1999
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