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9. INTERFACE MODE
(2) When command data update cycle = interrupt output cycle
(a) When command data update cycle is control cycle × 1, and interrupt out cycle is control cycle × 1.
Handler
sscIfmRenewLatestBufferEx function
sscSetCommandBitSignalEx function
(SSC_CMDBIT_SYS_HMA)
User program
processing
Control cycle
Interrupt signal (IRQ)
System program
processing
Handler
Command buffer 0
write
During user program
memory access (HMA)
During system program
memory access (BMA)
Control on
host controller
side
Control on
position board side
Realtime
processing
(Note 1)
(Command read)
System
program
occupy period
User program occupy period
(Less than control cycle/2)
Command data update cycle=interrupt output cycle
Background processing
(Note 2)
Realtime
processing
(Note 1)
(Command read)
Note 1. For real time processing, the execution of command read, high speed monitor, and communication with servo amplifier within
the control cycle are guaranteed processes.
2. For background processing, the execution of monitor, parameter read/write within the control cycle are not guaranteed
processes.
(b) When command data update cycle is control cycle × n, and interrupt output cycle is control cycle × n.
The following is an example of when command data update cycle = interrupt output cycle = control cycle
× 2.
Handler
sscIfmRenewLatestBufferEx function
sscSetCommandBitSignalEx function
(SSC_CMDBIT_SYS_HMA)
User program
processing
Control cycle
Interrupt signal (IRQ)
System program
processing
Handler
Command buffer 0
write
During user program
memory access (HMA)
During system program
memory access (BMA)
Control on
host controller
side
Control on
position board side
Realtime
processing
(Note 1)
(Command read)
System
program
occupy period
User program occupy period
(Less than control cycle/2)
Command data update cycle=interrupt output cycle
Background
processing
(Note 3)
Realtime
processing
(Note 1)
(Command read)
Background
processing
(Note 3)
Realtime
processing
(Note 2)
Note 1. For real time processing, the execution of command read, high speed monitor, and communication with servo amplifier within
the control cycle are guaranteed processes.
2. Reading of command is not performed for this real time process. (During system program memory access (BMA) does not turn
on)
3. For background processing, the execution of monitor, parameter read/write within the control cycle are not guaranteed
processes.