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Preliminary Information MT90840
2-237
Figure 3 - Serial Port Interface Functional Timing
Figure 4 - Parallel Data Port Functional Timing
C4/8R1&2
Serial I/O
2 Mbps
Serial I/O
4 Mbps
Frame Boundary Established by
F0
Ch. 31 Bit 1
Ch. 31 Bit 0
Ch. 0 Bit 7
Ch. 0 Bit 6
Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5
ch.127
Serial I/O
8 Mbps
(8 MHz)
C4/8R1&2
(4 MHz)
b3
ch.127
b2
ch.127
b1
ch.127
b0
ch. 0
b7
ch. 0
b6
ch. 0
b5
ch. 0
b4
Frame Boundary Established by PPFRi
PCKR
PPFRi
PDi0-7
Ch. n-2 Ch. n-1 Ch. n Ch. 0 Ch. 1 Ch. 2
Frame Boundary Established by PPFTi/o
PCKR or PCKT
PPFTi/o
PDo0-7
Ch. 0 Ch. 1 Ch. 2
Notes: In TM1, 2 and 4 PPFRi and PPFT are not simultaneous.
(PPFP bit =1)
Ch. n-2 Ch. n-1 Ch. n
Terminal count “n” = 2429, 2047, or 809.
(TCP bit = 0)