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MT90840 Preliminary Information
2-274
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
** Individual writes to Connection Memories will have Register Acknowledgment Delay. Burst writes to Connection Memories will have Read
Connection Memory Acknowledgment Delay.
AC Electrical Characteristics
†
- Intel/National- HPC Multiplexed Bus Mode
Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym Min Typ
‡
Max Units
Test Conditions/
Notes
1 ALE pulse width t
alw
10 ns
2 Address setup from ALE falling t
ads
5ns
3 Address hold from ALE falling t
adh
5ns
4RD Active after ALE falling t
alrd
15 ns
5 Data setup from DTA LOW on read t
ddr
0nsC
L
=150 pF on DTA,
and 30 pF on AD0-7.
6 CS hold after RD/WR t
csrw
0ns
7CS setup from RD t
csr
0ns
8 Data hold after RD t
dhr
10
15
22
30
ns
ns
C
L
=30 pF
C
L
=150 pF
9 WR delay after ALE falling t
alwr
15 ns
10 CS setup from WR t
csw
0ns
11 Data setup from WR
t
dsw
10 ns
12 Data hold after WR Inactive t
dhw
0ns
13 RD/WR Inactive to ALE Falling Edge t
rst
23 ns
14 Acknowledgment hold time t
akh
020nsC
L
=150 pF, R
L
=1kΩ∗
15 Data Delay on Reading Registers t
rdd
47
68
ns
ns
C
L
=30 pF
C
L
=150 pF
16 Acknowledgment Delay
Reading Registers
Acknowledgment Delay
Writing Registers
t
akd-rd
t
akd-wr
73
85
32
41
ns
ns
ns
ns
C
L
=30 pF
C
L
=150 pF
C
L
=30 pF
C
L
=150 pF
17 Acknowledgment Delay - Memories:
Reading TP Data Memory
Reading RP Data Memory
Reading TP Connection Memory
Reading RP Connection Memory
Writing TP Connection Memory**
Writing RP Connection Memory**
t
akd-mem
244
122
1 clock
cycle
244
t
akd-wr
t
akd-wr
488
366
2 clock
cycles
488
1306
1062
3 clk cyc +
t
akd-rd
817
3 clk cyc +
t
akd-wr
774
ns
ns
ns
ns
1 to 5 C4 cycles +
register t
akd-rd
.5 to 4 C4 cycles +
register t
akd-rd
1 to 3 PCKT/R cycles
+ register t
akd-rd
1 to 3 C4 cycles +
register t
akd-rd
Up to 3 PCKT/R cyc.
+ register t
akd-wr
Up to 3 C4 cycles +
register t
akd-wr