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Preliminary Information MT90840
2-233
Pin Description
Pin #
Name Description
84 100
343DS/RD Data Strobe/Read (Input). In Motorola multiplexed-bus mode this pin is DS, an
active high input which works with CS to enable read and write operation. In Intel/
National multiplexed-bus mode this pin is RD, an active low input which enables a
read-cycle and configures the data bus lines (AD0-AD7) as outputs.
4 44 AS/ALE Address Strobe / Address Latch Enable (Input). Falling edge is used to sample
address into the Address Latch circuit.
545 CS Chip Select (Input). Active low input enabling a microprocessor read or write of
control or status registers.
646 DTA Data Acknowledgment (Active Low Output). Indicates that a data bus transfer is
complete. When the bus cycle ends, this pin drives HIGH and then tri-states,
allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is
required to hold a HIGH level when the pin is tri-stated. Note that CPU read/writes
from/to the Data and Connection memories occur on the serial or parallel port
clock edges, and DTA will not change state if the clock is halted.
7 47 IRQ Interrupt Request (Active High Output). Output indicates that the MT90840 has
detected an alarm condition. The indication of the specific condition can be read in
the ALS (Alarm Status) Register. The CPU should read ALS, identify the source for
the interrupt and then rewrite the mask bits to re-enable the IRQ signal.
8 48 RES RESET (Schmitt Input). Asynchronous device reset. A logic-high signal should be
applied during power-up to bring the MT90840 internal circuitry to a defined state.
Serial and parallel TDM outputs (STo0-7, STi0-7, and PDo0-7) are held in
high-impedance state after reset until programmed otherwise. This input must be
held low during normal operation.
949 ICInternal Connection. The user must connect this pin to V
SS
. This pin must remain
low for the MT90840 to function normally, and to comply with IEEE 1149 (JTAG)
boundary scan requirements. This pin is pulled low internally when not driven.
10,
26,
27
1-4,
27-31
50-54
76-80
NC No Connection.
13-20 57-64 STi0-STi7 Serial Inputs 0 to 7 (Bidirectional). Serial TDM data-streams at 2.048, 4.096 or
8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For 2.048 and
4.096 Mbps applications, streams STi0-STi7 can be used, while for 8.192 Mbps,
only streams STi0-STi3 are used (512 channel limit). These eight bidirectional
lines can be programmed as inputs (default) or outputs on a per-channel basis.
21 65 C4/8R1 Serial Clock Reference Input 1. When enabled by the C4/8R bit (high) in the TIM
Register, this input receives the 4.096 or 8.192 MHz serial port clock reference. If
the C4/8R bit is set low, or if the INTCLK bit is set high, this input is ignored by the
MT90840.
In Timing Mode 1 (TM1), or at 8.192 MHz, the C4/8 input is used directly to shift
data in and out of the serial port.
In Timing Mode 2 (TM2) at 4.096 MHz, the C4 input from an external clock source
(e.g. a PLL locked to an 8 kHz reference) is phase-corrected by the MT90840, and
used to generate the serial port SPCKo and F0 outputs.
In Timing Modes 3 and 4 (TM3 and TM4) this input is not used.
For more details on the use of this signal, see the description of Timing Mode 1
and Timing Mode 2.