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Preliminary Information MT90840
2-273
Figure 29 - Parallel Port in Timing Mode 4
Figure 30 - Phase Variation Between C4/8R1 & C4/8R2 and PCKT Inputs for TM1 Operation
Figure 31 - Phase Variation Between C4 and PCKR Inputs for TM2 Operation
PPFRi
PPFT
PCKR
TCP = 0
PPFT
TCP = 1
Note: For the PPFT depicted above, PPFP = HIGH. If PPFP is LOW, the PPFT line will have negative pulse polarity.
t
df
t
df
PCKT
C4/8R1 or C4/8R2
PPFTo
t
pv
(ST-BUS Mode)
t
pv
PDo7-0
0nn-1 1 2n-2
Note: The MT90840 will correct phase relation in TM1 by moving PPFTo (by moving F0o in TM2 andTM3).
Ch. 3 Bit 1 Ch. 3 Bit 0 (4 Mbps) Ch. 4 Bit 7
STo (4 Mbps)
PCKR
SPCKo
PPFRi
t
pv
(ST-BUS Mode)
t
pv
PDi7-0
0nn-1 1 2
Note: The MT90840 will correct phase relation in TM2 by inverting SPCKo w.r.t. C4/8R1 or C4/8R2.
Ch. 61 Bit 2 Ch. 61 Bit 1 (4 Mbps) Ch. 61 Bit 0
STo (4 Mbps)