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MT90840 Preliminary Information
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Table 1 - MT90840 Throughput Delay Summary
Naming rules:
ELD: ELastic Delay, measured from PPFRi to F0i (4.4 to 129.4 µsec).
P/S:Parallel-to-Serial data path.
Pi:Parallel Input channel time, expressed in delay after PPFRi (0 to 125 µsec).
Po:Parallel Output channel time, expressed in delay after PPFTi/o (0 to 125 µsec).
S/P:Serial-to-Parallel data path.
Si:Serial Input channel time, expressed in delay after F0i/o (0 to 125 µsec).
So: Serial Output channel time, expressed in delay after F0i/o (0 to 125 µsec).
Transmission:The delay due to electronic circuits and physical media connecting the parallel ports of two MT90840s. (Assumed to be
negligible in TM3.)
Note 1: Exact P/S or S/P delay depends on relative positions of PPFRi and F0 +/- 120 nsec tolerance).
Note 2: Actual TM1 P/S and P/P delay depends on elastic position of PPFRi with respect to F0i (see ELD definition).
Note 3: Bypass delay in TM2: PPFT and PDo ch.0 are co-incident with PDi ch.235 at 19.44 MHz, ch.199 at 16 MHz, and ch.80 at 6.48
MHz. (TCP = 1 delays PDo ch.0 an extra half clock-cycle in TM2).
Note 4: “Round-trip” delay from/to serial ports with the same F0 is always an integral number of frames (plus switching: So - Si).
Mode Data Rates Minimum Delay Total Throughput Delay
TM1, TM2,
or TM3 S/P
All Dmin = 7.7 µsec
Note 1
D = Dmin + 1 frame + Po - Si = 132.7 µsec + Po - Si
Min. 7.7 µsec, Avg. 133 µsec, Max. 258 µsec
TM1P/S All Dmin = ELDmin
= 4.4 µsec
Note 2
D = 1 frame + ELD + So - Pi = 125 µsec + ELD + So - Pi
Min. 4.4 µsec, Max. 379 µsec
TM2 P/S All Dmin = 4.3 µsec
Note 1
D = Dmin + 1 frame + So - Pi = 129.3 µsec + So - Pi
Min. 4.3 µsec, Avg. 129 µsec, Max. 254 µsec
TM3 P/S All Dmin = 1 frame -
7.7 µsec
= 117.3 µsec
T = Dmin + 1 frame + So - Pi = 242.3 µsec + So - Pi
Min. 117 µsec, Avg. 242 µsec, Max. 367 µsec
TM1 P/P
(Bypass)
All Dmin = 12 µsec +
1 frame
= 137 µsec
Note 2
D = 7.7 µsec + 1 frame + ELD
Min.137 µsec, Max. 262 µsec
TM2 P/P
(Bypass)
19.44 Mbyte/s
16.384 Mbyte/s
6.480 Mbyte/s
Note 3
D = {235 or 235.5} PCKR cycles = 12 µsec
D = {199 or 199.5} PCKR cycles = 12 µsec
D = {80 or 80.5} PCKR cycles = 12 µsec
TM4 P/P
(Switching)
19.44 & 16.384
Mbyte/s
Dmin = {3.5 or 4}
PCKR cycles
(TCP bit = 1 or 0)
D = Dmin + 1 frame + Po - Pi
Min. < 0.3 µsec, Avg. 125 µsec, Max. 250 µsec
TM1 S/P +
TM2 P/S
All Dmin = 12 µsec +
1 frame
= 137 µsec
D = 12 µs + 2 frames + Transmission + So - Si
= 262 µsec + Transmission + So - Si
TM2 S/P +
TM1 P/S
All Dmin = 12 µsec +
1 frame
= 137.4 µsec
D = 12 µsec + 2 frames + Transmission + ELD + So - Si
= 262 µsec + Transmission + ELD + So - Si
TM1 S/P +
TM2 P/S +
TM2 S/P +
TM1 P/S
All Dmin = 4 frames
= 500 µsec
D = (2 X 12) µsec + 4 frames + 2 X Transmission + ELD
+ So - Si = {5 or more integral frames} + So - Si
(Note 4)
TM1 S/P +
TM2
Bypass +
TM1 P/S
All Dmin = 2 frames
= 250 µsec
D = (3 X 12) µsec + 2 frames + 2 X Transmission + ELD
+ So - Si
= {3 or more integral frames} + So - Si
(Note 4)
TM3 S/P +
TM3 P/S
All Dmin = 250 µsec D = (7.7 + 117.3) µsec + 2 frames + So - Si
= 375 µsec + So - Si
Min. 250 µsec, Avg. 375 µsec, Max. 500 µsec (Note 4)