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B-9
SIGNAL DESCRIPTIONS
HOLD# I Bus Hold Request
An external device uses this active-low input signal to request control of the
bus. This pin functions as HOLD# only if the pin is configured for its special
function (see “Bidirectional Port Pin Configurations” on page 7-7) and the bus-
hold protocol is enabled. Setting bit 7 of the window selection register (WSR)
enables the bus-hold protocol.
HOLD# is multiplexed with P2.5.
INST O Instruction Fetch
This active-high output signal is valid only during external memory bus cycles.
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector
fetches and chip configuration byte reads. INST is low during internal memory
fetches.
NMI I Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable
interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for
greater than one state time to guarantee that it is recognized.
ONCE I On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the device into
on-circuit emulation (ONCE) mode. This mode puts all pins into a high-
impedance state, thereby isolating the device from other components in the
system. The value of ONCE is latched when the RESET# pin goes inactive.
While the device is in ONCE mode, you can debug the system using a clip-on
emulator. To exit ONCE mode, reset the device by pulling the RESET# signal
low. To prevent accidental entry into ONCE mode, connect the ONCE pin to
V
SS
.
P1.7:0 I/O Port 1
This is a standard, bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 1 is multiplexed as follows: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2,
P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.
P2.7:0 I/O Port 2
This is a standard bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 2 is multiplexed as follows: P2.0/TXD, P2.1/RXD, P2.2/EXTINT0,
P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and P2.7/CLKOUT.
P3.7:0 I/O Port 3
This is an 8-bit, bidirectional, standard I/O port.
Port 3 is multiplexed as follows: P3.0/CS0#, P3.1/CS1#, P3.2/CS2#,
P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and P3.7/EXTINT3.
P4.3:0 I/O Port 4
This is a 4-bit, bidirectional, standard I/O port with high-current drive capability.
Port 4 is multiplexed as follows: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2.
P4.3 is not multiplexed.
Table B-3. Signal Descriptions (Continued)
Name Type Description