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ADSP-21369 EZ-KIT Lite Evaluation System Manual 2-25
EZ-KIT Lite Hardware Reference
JTAG Header (P2)
The JTAG header (P2) is the connecting point for a JTAG in-circuit emu-
lator pod. When an emulator is connected to the JTAG header, the USB
debug interface is disabled.
L
Pin 3 is missing to provide keying. Pin 3 in the mating connector
should have a plug.
L
When using an emulator with the EZ-KIT Lite board, follow the
connection instructions provided with the emulator.
Part Description Manufacturer Part Number
14-pin IDC Header Berg 54102-T08-07