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2-2 ADSP-21369 EZ-KIT Lite Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board (Figure 2-1).
The EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-21369 processor. The processor core is powered at 1.3V, and the
IO is powered at 3.3V.
Figure 2-1. System Architecture Block Diagram
ADSP-21369
DSP
JTAG
Header
Power Regulation
PBs (4)
J
T
A
G
P
o
r
t
A5V
+
7
.
0
V
C
o
n
n
e
c
t
o
r
Expansion
Connectors
Type A
1M x8
Flash
24.576 MHz
Oscillator
External
Port
3.3V
Ster eo Out RCA
Jacks (4x2)
Stereo In RCA
Jacks (2x1)
DAI
1.3V
AD1835
CODE C
DPI
SPI FLASH
512k x 8
SRAM
SPDIF Out
Ph o no
FLAGs
0,1,and 3
2
2
He ad phone
Jack
Reset PB
SPDIF In
Ph o no
4M x 32
SDRAM
LEDs
(8)
5
DPI
Conn
DAI
Conn
RS
232
Conn
ADM 3 20 2
EL VIS
Conn
1
2