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Epson Research and Development Page 21
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
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Figure 3-4 Typical System Diagram (Hitachi SH-3 Bus)
S1D13708
FPLINE
FPFRAME
FPSHIFT
DRDY
FPDAT[17:0]
FPLINE
FPFRAME
FPSHIFT
DRDY
D[17:0]
18-bit
SH-3
BUS
RESET#
WE0#
D[15:0]
BS#
RD/WR#
RD#
WAIT#
A[16:0]
CKIO
WE0#
RD/WR#
AB[16:0]
DB[15:0]
WE1#
BS#
RD#
M/R#
CS#
CLKI
WAIT#
RESET#
A[25:17]
CSn#
WE1#
GPO0
CLKI2
Oscillator
TFT
Display
Bias Power
Decoder