Epson Research and Development Page 109
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
6.4.16 TFT Type 4 Panel Timing
Figure 6-46 TFT Type 4 Panel Timing
VDP = Vertical Display Period
= VDP Lines
VNDP = Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines if negative add VT
HDP = Horizontal Display Period
= HDP Ts
HNDP = Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - (HPS + 1) + 5 Ts if negative add HT
HNDP2 = Horizontal Non-Display Period 2
= (HPS + 1) - (HDP + HDPS + 5) Ts if negative add HT
FPFRAME
FPLINE
LINE1 LINE480
1-1 1-2 1-640
FPLINE
FPSHIFT
DRDY
FPDAT[17:0]
VDP
DRDY
Note: DRDY is used to indicate the first pixel
Example Timing for 12-bit 640x480 panel
VNDP
2
HDP
HNDP
1
HNDP
2
LINE480
VNDP
1
FPDAT[17:0]
invalid
invalid
