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Page 114 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
XTAL REG[CAh] bit 1 = 1, REG[05h] = 03h
XTAL ÷
2 REG[CAh] bit 1 = 1, REG[05h] = 13h
XTAL ÷
3 REG[CAh] bit 1 = 1, REG[05h] = 23h
XTAL ÷
4 REG[CAh] bit 1 = 1, REG[05h] = 33h
XTAL ÷
8 REG[CAh] bit 1 = 1, REG[05h] = 43h
Table 7-3: PCLK Clock Selection (Continued)
Source Clock Options PCLK Selection