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Epson Research and Development Page 159
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bits 4-3 VCLK Hold Bits [1:0]
These bits control the TFT Type 2 AC timing parameter from the rising edge of STB to the
falling edge of VCLK. The parameter is selected as follows. For all other panel interfaces
it has no effect.
bits 1-0 VCLK Setup Bits [1:0]
These bits control the TFT Type 2 AC timing parameter from the rising edge of VCLK to
the rising edge of STB. The parameter is selected as follows. For all other panel interfaces
it has no effect.
TFT Type 2 VCLK Configuration Register
REG[D0h] Read/Write
n/a VCLK Hold bits 1-0 n/a VCLK Setup bits 1-0
7 6 543210
Table 8-21: VCLK Hold
REG[D0h] bits 1-0 VCLK Hold (in PCLKs)
00 7
01 9
10 12
11 16
Table 8-22: VCLK Setup
REG[D0h] bits 4-3 VCLK Setup (in PCLKs)
00 7
01 9
10 12
11 16