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S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
Figure 6-43 TFT Type 2 Vertical Timing
1. Ts = pixel clock period
2. t1typ = (REG[19h] bits 1-0, REG[18h] bits 7-0) +1
3. t4typ = (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0)
4. t5typ = (REG[1Dh] bits 1-0], REG[1Ch] bits 7-0) + 1
Table 6-37: TFT Type 2 Vertical Timing
Symbol Parameter Min Typ Max Units
t1
Vertical total period 8 note 1 1024 Lines
t2
FPFRAME pulse width 1 Lines
t3
GPIO3 rising edge to FPFRAME rising edge 0 Ts (note 1)
t4
Vertical display start position 0 note 2 1024 Lines
t5
Vertical display period 1 note 3 1024 Ts
FPFRAME
GPIO3
(Odd Frame)
GPIO2
D[17:0]
(Alternate Timing)
Line2Line1
t1
t2
t3
t4 t5
(Even Frame)
Last
(STV)
(STH)
(POL)
GPIO2
(POL)
GPIO2
(POL)
