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Page 164 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bit 5-4 PCLK2 Divide Rate Bits [1:0]
These bits specify the divide rate for PCLK2. This register is used for the TFT Type 3
Interface and has no effect for all other panel interfaces.
bits 3-0 PCLK1 Divide Rate Bits [3:0]
These bits specify the divide rate for PCLK1. This register is used for the TFT Type 3
Interface and has no effect for all other panel interfaces.
TFT Type 3 PCLK Divide Register
REG[DCh] Read/Write
n/a PCLK2 Divide Rate PCLK1 Divide Rate
7 6543210
Table 8-25: GPO2 PCLK2 Divide Rate
REG[DBh] bits 5-4 PCLK2 Divide Rate
00 64
01 128
10 256
11 512
Table 8-26: GPO1 PCLK1 Divide Rate
REG[DBh] bits 3-0 GPO1 PCLK1 Divide Rate
0000 2
0001 4
0010 8
0011 16
0100 32
0101 64
0110 128
0111 256
1000 512
1001 1024
1010 2048
1011 4096
1100 8192
1101 16384
1110 32768
1111 65536