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Page 118 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
8 Registers
This section discusses how and where to access the S1D13708 registers. It also provides
detailed information about the layout and usage of each register.
8.1 Register Mapping
The S1D13708 registers are memory-mapped. When the system decodes the input pins as
CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by
A[16:0].