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Overview........................................................................................................................................ 18
State Analysis Operation – Read and Writes above 667MT/s....................................................................18
State Analysis Operation – Read and Write at 667MT/s or slower............................................................19
State Analysis Operation – Read or Write at 800MT/s ..............................................................................19
The process for setting sampling positions at speeds of 800MT/s:........................................... 20
State analysis calibration procedure ...........................................................................................................21
Adjusting the sampling positions with controlled stimulus ...................................................... 24
State Display.................................................................................................................................. 26
DDR2 Protocol Checking and Performance Tool (FS1140) ..............................................27
FS1140 Installation and Licensing .............................................................................................. 27
Loading the FS1140...................................................................................................................... 27
Setting up the FS1140 DDR2 Tool............................................................................................... 28
Functional and Performance Analysis – NOTE: The Functional Performance portion of this
software will NOT work with 2 FRAME configurations .......................................................... 29
Statistics......................................................................................................................................................29
Errors..........................................................................................................................................................29
Export.........................................................................................................................................................30
Repetitive Run............................................................................................................................................30
Timing Analysis ............................................................................................................................ 30
Export.........................................................................................................................................................30
Appendix................................................................................................................................32
FS2334 Signal to Logic Analyzer Connector and Channel Mapping ...................................... 32