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8 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express
UG343 June 27, 2008
Chapter 1: Introduction
R
performance, pipelined FPGA designs using Xilinx implementation software and User
Constraints Files (UCF) is recommended.
Additional Core Resources
For detailed information and updates about the core, see the following documents,
available from the Block Plus for PCIe
product page
unless otherwise noted.
• LogiCORE IP Endpoint Block Plus for PCI Express Data Sheet
• LogiCORE IP Endpoint Block Plus for PCI Express User Guide
• LogiCORE IP Endpoint Block Plus for PCI Express Release Notes (available from the core
directory after generating the core)
• Virtex-5
Integrated Endpoint Block for PCI Express Designs User Guide (UG197)
Additional information and resources related to the PCI Express technology are available
from the following web sites:
• PCI Express at PCI-SI
G
• PCI Express Developer’s Forum
Technical Support
For technical support, go to www.xilinx.com/support. Questions are routed to a team of
engineers with expertise using the Endpoint Block Plus for PCI Express core.
Xilinx provides technical support for use of this product as described in the LogiCORE IP
Endpoint Block Plus for PCI Express User Guide and the LogiCORE IP Endpoint Block Plus for
PCI Express Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support
of this product for designs that do not follow these guidelines.
Feedback
Xilinx welcomes comments and suggestions about the core and the accompanying
documentation.
Core
For comments or suggestions about the core, please submit a WebCase from
www.xilinx.com/support
. Be sure to include the following information:
• Product name
• Core version number
• Explanation of your comments