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18 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express
UG343 June 27, 2008
Chapter 3: Quickstart Example Design
R
Simulating the Example Design
The example design provides a quick way to simulate and observe the behavior of the core.
The simulation environment provided with the Block Plus core performs simple memory
access tests on the PIO example design. Transactions are generated by the Downstream
Port Model and responded to by the PIO example design.
• PCI Express Transaction Layer Packets (TLPs) are generated by the test bench transmit
user application (
pci_exp_usrapp_tx). As it transmits TLPs, it also generates a log file,
tx.dat.
• PCI Express TLPs are received by the test bench receive user application
(
pci_exp_usrapp_rx). As the user application receives the TLPs, it generates a log file,
rx.dat.
For more information about the test bench, see Appendix B, “Downstream Port Model Test
Bench,” in the LogiCORE IP Endpoint Block Plus for PCI Express User Guide.
Setting up for Simulation
To run the gate-level simulation you must have the Xilinx Simulation Libraries compiled
for your system. See the Compiling Xilinx Simulation Libraries (COMPXLIB) in the Xilinx
ISE Synthesis and Verification Design Guide, and the Xilinx ISE Software Manuals and Help.
Documents can be downloaded from w
ww.xilinx.com/support/software_manuals.htm.
Simulator Requirements
Virtex-5 device designs require either a Verilog LRM-IEEE 1364-2005 encryption-compliant
simulator or a SWIFT-compliant simulator.
• For a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator, ModelSim v6.3c
is currently supported.
• For a SWIFT-compliant simulator, Cadence IUS v6.1 and Synopsys VCS 2006.06-SP1
are currently supported.
Note for Cadence IUS users: The work construct must be manually inserted into your
CDS.LIB file as shown below.
DEFINE WORK WORK
Running the Simulation
For Cadence IUS
The simulation scripts provided with the example design support pre-implementation
(RTL) simulation. The existing test bench can be used to simulate with a post-
implementation version of the example design.
The pre-implementation simulation consists of the following components:
• Verilog or VHDL model of the test bench
• Verilog or VHDL RTL example design
• The Verilog or VHDL model of the Endpoint Block Plus for PCI Express
1. To run the simulation, go to the following directory:
<project_dir>/<component_name>/simulation/functional