Filter
Top Products
24 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express
UG343 June 27, 2008
Chapter 3: Quickstart Example Design
R
simulation/dsport
The dsport directory contains the data stream simulation scripts provided with the core.
simulation/functional
The functional directory contains functional simulation scripts provided with the core.
Table 3-8: dsport Directory
Name Description
<project_dir>/<component_name>/simulation/dsport
dsport_cfg.v[hd]
pci_exp_expect_tasks.v
pci_exp_1_lane_64b_dsport.v[hd]
pci_exp_4_lane_64b_dsport.v[hd]
pci_exp_usrapp_cfg.v[hd]
pci_exp_usrapp_com.v
pci_exp_usrapp_rx.v[hd]
pci_exp_usrapp_tx.v[hd]
xilinx_pci_exp_downstream_port.v[hd]
xilinx_pci_exp_dsport.v[hd]
test_interface.vhd
Downstream port model files.
Back to Top
Table 3-9: Functional Directory
Name Description
<project_dir>/<component_name>/simulation/functional
board_rtl_x01_v4fx.f
board_rtl_x04_v4fx.f
board_rtl_x08_v4fx.f
board_rtl_x01_v4fx_ncv.f
board_rtl_x04_v4fx_ncv.f
board_rtl_x08_v4fx_ncv.f
board_rtl.f
List of files for RTL simulations.
simulate_mti.do
Simulation script for ModelSim.
simulate_ncsim.sh
Simulation script for Cadence IUS.
simulate_vcs.sh
Simulation script for VCS.
xilinx_lib_vcs.f
xilinx_lib_vnc.f
Points to the required SmartModel.
Back to Top