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Video Mode Timing—AMLCD Video Mode, VGA, Fixed
Item Description Min. Max. Units
1 HS low time 2 200 VCLK periods
2 HS to VCLK phase
difference
10 VCLK period - 10 nsec
5 VCLK frequency 28.33 MHz
6 R/G data set up to VCLK 5 nsec
7 R/G data hold from VCLK 10 nsec
8 VS low width 2 34 HS periods
9 VS to HS phase difference 0 HS period – HS low time nsec
10 Vertical start position After 34 HS rising edges
HS period 30 usec
VS period 515 560 HS periods
HS
VCLK
R/G dat
a
VS
HS
Horizontal Timing
Vertical Timin
g
data for first pixel
9
8
6 7
5
10
1
horizontal invalid data period
clock edge C1
first valid clock =
clock edge C104
R/G dat
a
vertical invalid data period
data for first line
Line 1
Line 2
Line N
2
EL320.240-FA3 Operations Manual Page 19 of 25