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Video Mode Timing—AMLCD Video Mode, QVGA
Item Description Min. Max. Units
1 HS low time 2 200 VCLK periods
2 HS to VCLK phase difference 10 VCLK period - 10 nsec
3 HS to DE phase difference 2 HS period - 340 VCLK periods
4 DE set up time 5 VCLK period - 10 nsec
5 VCLK frequency 7 MHz
6 R/G data set up to VCLK 5 nsec
7 R/G data hold from VCLK 10 nsec
8 VS low width 2 34 HS periods
9 VS to HS phase difference 0 HS period – HS low
time
nsec
10 Vertical start position After 7 HS rising edges
DE high time 2 HS period - 10 VCLK periods
HS period 50 usec
VS period 251 280 HS periods
HS
VCL
K
R/G dat
a
VS
HS
Horizontal Timing
Vertical Timin
g
data for first pixel
9
8
6 7
5
10
1
horizontal invalid data period
DE
3
4
R/G dat
a
vertical invalid data period
data for first line
Line 1
Line 2
Line N
2
EL320.240-FA3 Operations Manual Page 16 of 25