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Philips Semiconductors
User’s Manual - Preliminary -
P89LPC901/902/903
FLASH PROGRAM MEMORY
2003 Dec 8 93
14. FLASH PROGRAM MEMORY
General description
The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read and
written as bytes. On-chip erase and write timing generation contribute to a user-friendly programming interface. The cell is
designed to optimize the erase and programming mechanisms. The P89LPC901/902/903 uses V
DD
as the supply voltage to
perform the Program/Erase algorithms. Additionally, serial programming using commercially available programmers provides a
simple inteface to achieve in-circuit programming.The P89LPC901/902/903 Flash reliably stores memory contents after 100,000
erase and program cycles (typical).
Features
• IAP-Lite allows individual and multiple bytes of code memory to be used for data storage.
• Programming and erase over the full operating voltage range
• Read/Programming/Erase using IAP-Lite
• Any flash program operation in 2 ms (4ms for erase/program)
• Serial programming with industry-standard commercial programmers allows in-circuit programming.
• Programmable security for the code in the Flash for each sector.
• >100,000 typical erase/program cycles for each byte.
• 256 byte sector size, 16 byte page size
• 10-year minimum data retention.
Introduction to IAP-Lite
The Flash code memory array of this device supports IAP-Lite programming and erase functions. Any byte in a non-secured
sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non-volatile data stor-
age. In addition, the user’s code may access additional flash elements. These include UCFG1, the Boot Vector, Status Bit,
security bytes, and signature bytes. Access of these elements uses a slightly different method than that used to access the user
code memory.
Using Flash as data storage
IAP-Lite provides an erase-program function that makes it easy for one or more bytes within a page to be erased and pro-
grammed in a single operation without the need to erase or program any other bytes in the page. IAP-Lite is performed in the
application under the control of the microcontroller’s firmware using four SFRs and an internal 16-byte "page register" to facili-
tate erasing and programming within unsecured sectors. These SFRs are:
• FMCON (Flash Control Register). When read, this is the status register. When written, this is a command register. Note that
the status bits are cleared to ’0’s when the command is written.
• FMDATA (Flash Data Register). Accepts data to be loaded into the page register.
• FMADRL, FMADRH (Flash memory address low, Flash memory address high). Used to specify the byte address within the
page register or specify the page within user code memory.
The page register consists of 16 bytes and an update flag for each byte. When a LOAD command is issued to FMCON the page
register contents and all of the update flags will be cleared. When FMDATA is written, the value written to FMDATA will be
stored in the page register at the location specified by the lower 6 bits of FMADRL. In addition, the update flag for that location
will be set. FMADRL will auto-increment to the next location. Auto-increment after writing to the last byte in the page register will
"wrap -around" to the first byte in the page register, but will not affect FMADRL[7:4]. Bytes loaded into the page register do not
have to be continuous. Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writ-