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Philips Semiconductors
User’s Manual - Preliminary -
P89LPC901/902/903
CLOCKS
2003 Dec 8 33
Low Power Select (P89LPC901)
The P89LPC901 is designed to run at 12MHz (CCLK) maximum. However, if CCLK is 8MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to a ’1’ to lower the power consumption further. On any reset, CLKLP is ’0’ allowing highest performance.
This bit can then be set in software if CCLK is running at 8MHz or slower.