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SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 41
UG154 March 24, 2008
Demonstration Test Bench
R
Testcase Module
The testcase module generates data and sends it to the stimulus module, which in turn
transmits data to the Sink core and status to the Source core. The following data is created
in the testcase module:
• Static configuration signals
• SPI-4.2 and demonstration test bench requests
• Source core status and Sink core data
Figure 4-2 shows the interface between the testcase and stimulus modules.
The static configuration signals are set when the SPI-4.2 core is generated; these signals can
also be modified in circuit. The description of these signals can be found in the SPI-4.2 Core
User Guide.
The status and data generation is simplified by instantiating the procedures module and
calling the functions contained in the module. This allows the testcase module to be
completely asynchronous, as all of the clocking is done in the
procedures module.
DATA_NUM_TRAIN_SEQ Integer 3 <0 - 255> Sets the number of complete training patterns that
the demonstration test bench has to receive on
TDat (upon startup) before it stops sending
framing sequences on TStat. Once this happens,
the demonstration test bench begins sending
valid status.
TDCLK_PERIOD Time 2.86 ns
<time>
Sets the period of the SysClk signal, which is used
by the Source core to generate TDClk. Value must
be greater than or equal to 2.00 ns (≤ 500 MHz).
RDCLK_PERIOD Time 2.86 ns
<time>
Sets the period of the RDClk signal and the half-
period of the RDClk2x signal. Value must be
greater than or equal to 2.00 ns (≤ 500 MHz).
USERCLK_PERIOD Time 5.71 ns
<time>
Sets the period of the UserClk, used for the
loopback interface to the cores and programming
of the calendars. Value must be greater than or
equal to 4.00 ns (≤ 250 MHz).
TFF Time 500 ps
<time>
Clock-to-out time used by logic in the
demonstration test bench
Table 4-10: Testcase Package User-Defined Constants (Continued)
Name
Constant
Type
Default Value
(Range)
Description