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CONTROL REGISTERS S3C8245/P8245/C8249/P8249
4-10
IMR — Interrupt Mask Register DDH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
nRESET Value x x x x x x x x
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.4–0.7
0
Disable (mask)
1
Enable (unmask)
.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.0–0.3
0
Disable (mask)
1
Enable (unmask)
.5 Interrupt Level 5 (IRQ5) Enable Bit; Watch Timer Overflow
0 Disable (mask)
1 Enable (unmask)
.4 Interrupt Level 4 (IRQ4) Enable Bit; SIO Interrupt
0 Disable (mask)
1 Enable (unmask)
.3 Interrupt Level 3 (IRQ3) Enable Bit; Timer 1 Match/Capture or Overflow
0 Disable (mask)
1 Enable (unmask)
.2 Interrupt Level 2 (IRQ2) Enable Bit; Timer 0 Match
0 Disable (mask)
1 Enable (unmask)
.1 Interrupt Level 1 (IRQ1) Enable Bit; Timer B Match
0 Disable (mask)
1 Enable (unmask)
.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer A Match/Capture or Overflow
0 Disable (mask)
1 Enable (unmask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.