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S3C8245/P8245/C8249/P8249 CLOCK CIRCUIT
7-3
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in the bank 0 of set 1, address D4H. It is read/write
addressable and has the following functions:
— Oscillator frequency divide-by value
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
System Clock Control Register (CLKCON)
D4H, Set 1, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Not used (must keep always 0) Not used (must keep always 0)
Divide-by selection bits for
CPU clock frequency:
00 = f
XX
/16
01 = f
XX
/8
10 = f
XX
/2
11 = f
XX
/1 (non-divided)
NOTE:
The fxx can be generated by both main-system and
sub-system oscillator therefore while main-system
stops peripherals can be operated by sub-system.
Figure 7-4. System Clock Control Register (CLKCON)