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Table of Tables
Table 1-1: Slim SATA SSD Features _____________________________________________ 10
Table 2-1: Maximum Sustained Read and Write: MB/sec and IOPS _____________________ 14
Table 2-2: Timing Specifications _________________________________________________ 14
Table 2-3: STANDBY IMMEDIATE Timings ________________________________________ 14
Table 2-4: Absolute Maximum Ratings ____________________________________________ 15
Table 2-5: Operating Voltage ___________________________________________________ 15
Table 2-6: Current Draw _______________________________________________________ 15
Table 2-7: Typical Power Consumption ___________________________________________ 16
Table 2-8: Temperature and Altitude Related Specifications ___________________________ 16
Table 2-9: Shock and Vibration Specifications ______________________________________ 17
Table 2-10: Reliability Specifications ______________________________________________ 17
Table 4-1: Serial ATA Connector Pin Signal Definitions _______________________________ 22
Table 4-2: Serial ATA Power Pin Definitions ________________________________________ 23
Table 5-1: ATA Feature Set ____________________________________________________ 24
Table 5-2: ATA Commands _____________________________________________________ 26
Table 5-3: S.M.A.R.T. Command Set _____________________________________________ 32
Table 5-4: Supported S.M.A.R.T. EXECUTE OFF-LINE IMMEDIATE Subcommands ________ 32
Table 5-5: Baseline S.M.A.R.T. Attribute Summary __________________________________ 34
Table 5-6: Baseline S.M.A.R.T. Attribute Details _____________________________________ 36
Table 5-7: S.M.A.R.T. Attribute Data Structure ______________________________________ 45
Table 5-8: S.M.A.R.T. Threshold Data Structure _____________________________________ 46
Table 6-1: Device Certifications _________________________________________________ 47
Table of Figures
Figure 1-1: High-Level Block Diagram for VRFEM1xxP _______________________________ 12
Figure 3-1: Dimensions ________________________________________________________ 21
Figure 4-1: Layout of Signal and Power Segment Pins ________________________________ 22
Figure 5-1: S.M.A.R.T. ECC and RAISE Error Summary ______________________________ 44
