ADSP-BF548 Processor Memory Hierarchy
2-2 Getting Started with ADSP-BF548 EZ-KIT Lite
ADSP-BF548 Processor Memory
Hierarchy
The ADSP-BF548 processor supports a ‘hierarchy’ of three synchronous
memories, where the term synchronous means that the memory operates in
step with the edges of the clock signal on whichever processor bus is used
to access the memory. Understanding the differences between the differ-
ent memories is an important aspect of high-performance application
development.
• Internal L1 memory. Consists of 196K bytes of SRAM within the
processor, split into several different areas. L1 memory is the high-
est-performing memory available to the Blackfin core and can be
accessed at core clock speeds. An application never stalls waiting
for a memory read/write in L1 or for an instruction fetched from
L1. Instructions (code) and data are held in separate areas of L1,
and part of each area can be set aside and used as a cache for the
lower level memories.
• Internal L2 memory. Consists of a single 128K byte area of SRAM
within the processor. L2 is somewhat lower-performing than L1,
requiring two core clock cycles for access. L2 also has longer laten-
cies than L1. Instructions and data can co-exist in L2 memory.
• External memory. Sometimes referred to as L3, this is DDR
SDRAM that exists external to the processor and can be found
mounted on the EZ-KIT Lite board. 64M bytes of DDR SDRAM
is supplied on the EZ-KIT Lite, but different sizes can be used on
custom hardware to suit your application’s specific needs, up to a
maximum of 512M bytes. External memory operates synchro-
nously with the processor’s system clock rather than the core clock,
causing access time to SDRAM to be relatively slower than to L1 or
L2 memory. Similar to L2, external memory can hold instructions
and data.
