DM9161B
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 40
Version: DM9161B-12-DS-F01
January 31, 2008
9.4.13 MII 10BASE-T Receive Nibble Timing Parameters
Symbol Parameter Min. Typ. Max. Unit Conditions
tRX
s
RXD [0:3], RXDV, RXER Setup To RXCLK High 5 - - ns
tRX
h
RXD [0:3], RXDV, RXER Hold From RXCLK High 5 - - ns
tRX
pd
RX+/- To RXD [0:3] Out (Rx Latency) - 7 - BT
t1 CRS Asserted To RXD [0:3], RXDV, RXER,Asserted 1 14 20 BT
t2 CRS De-asserted To RXD [0:3], RXDV,
RXER,De-asserted
- - 3 BT
t3 RXI In To CRS Asserted 1 2 4 BT
t4 RXI Quiet To CRS De-asserted 1 10 15 BT
9.4.14 MII 10BASE-T Receive Nibble Timing Diagram
RXCLK
t
2
t
1
t
TX
pd
RXD [0:3],
RXDV, RXER
CRS
RX+/-
t
RX
S
t
RX
h
t
4
t
3
9.4.15 Auto-negotiation and Fast Link Pulse Timing Parameters
Symbol Parameter Min. Typ.
Max. Unit Conditions
t1 Clock/Data Pulse Width - 100 - ns
t2 Clock Pulse To Data Pulse Period 55.5 62.5 69.5 us DATA = 1
t3 Clock Pulse To Clock Pulse Period 111 125 139 us
t4 FLP Burst Width - 2 - ms
t5 FLP Burst To FLP Burst Period 8 - 24 ms
- Clock/Data Pulses in a Burst 17 - 33 pulse
